1. Field of the Invention
The present invention relates to a semiconductor device such as a memory LSI of which a logic LSI (Logical Large Scale Integrated Circuit), a DRAM (Dynamic Random Access Memory), and an SRAM (Static Random Access Memory) are typical, an LSI configured by a bipolar transistor, or the like.
2. Description of the Related Art
In recent years, as a wiring structure of an LSI, a multi-level interconnection structure using a copper (Cu) damascene wiring (a copper wiring formed by a damascene process) has joined the mainstream due to the demands for making an LSI minute and low-resistant, and the like. Copper wiring generally has higher electro-migration (EM) tolerance at the wiring portion as compared with an aluminum wiring.
(1) However, for example, as shown in FIG. 1, copper wiring 1 has low adhesion with a stopper (an insulating layer) 2 made of SiN, SiCN, SiCO, SiC or the like which is formed on the copper wiring 1 as a layer for preventing copper from diffusing/being oxidized. Therefore, as shown by the arrow, it is the easiest for copper atoms to move at an interface between the copper wiring 1 and the stopper 2, and as a result, a void 3A is easily generated at the interface, and EM tolerance (lifetime) cannot be sufficiently improved.
To solve such a problem, for example, as shown in FIG. 2, there has been proposed a cap-metal technique in which metal (for example, Co, WP (Tungsten Phosphide), or the like) for improving the adhesion between the copper wiring 1 and the stopper 2 is provided therebetween. In accordance with this technique, the generation of a void at the interface between the copper wiring 1 and the stopper 2 can be suppressed, and the EM tolerance (lifetime) of the copper wiring can be improved.
However, in this technique, a metal 4 must be selectively formed on the copper wiring 1 by using, for example, a CVD method, an electrolytic plating method, or the like, and the problem that technical difficulty with respect to the manufacturing method is made high arises.
For example, as shown in FIG. 3, in accordance with a method in which the metal 4 is selectively made to grow on the copper wiring 1, it is difficult to uniformly form the metal 4 on the copper wiring 1, and there are cases in which pinholes 5 are formed, or metals 4′ are formed on portions other than the top of the copper wiring 1 (selectivity disorder). Further, for example, as shown in FIG. 4, in a method in which the metals 4 at the portions other than the top of the copper wiring 1 are removed by CMP after the metal 4 is formed on the entire portion including the top of the copper wiring 1, problems that the copper wiring 1 is exposed due to the metal 4 being overly shaved, or the like arise (over-shaving by CMP).
(2) Further, recently, for example, as shown in FIG. 5, it has been studied that a barrier metal 6 is formed by a CVD method which has high coverage performance, and which can form a thin film.
However, the barrier metal 6 formed by a CVD method has lower adhesion with respect to the copper wiring 1 as compared with that of a barrier metal formed by a PVD method. Therefore, as shown by the arrow, it is easier for copper atoms to move at the interface between the copper wiring 1 and the barrier metal 6, and as a result, a void 3B is easily generated at the interface, and the EM tolerance (lifetime) cannot be sufficiently improved.
In this way, conventionally, the adhesion between the copper wiring 1 and the stopper 2, and a deterioration in EM tolerance (lifetime) due to a deterioration in the adhesion between the copper wiring 1 and the barrier metal 6 have been the problems. However, the problems cannot be solved without any problem of process.
(3) Further, as another technique for improving an EM tolerance (lifetime), there is a technique in which an additive (for example, metal) for improving the adhesion with a stopper or a barrier metal is included in copper wiring. In this technique, for example, this additive is included in advance in a seed copper serving as a seed layer which will be undercoating at the time of copper plating, and the additive is added into the copper wiring at the same time when the copper wiring is formed.
However, a new problem that, if the additive is uniformly included in the entire copper wiring, the resistance of the copper wiring rises occurs. Namely, the reliability of the wiring (the improvement in the EM tolerance) and a signal delay (a deterioration in wiring resistance) establish the relationship of trade-off, and as a result, a high performance and high reliability multi-level interconnection structure cannot be provided.